Crystal film, crystal substrate, and semiconductor device

ABSTRACT

A crystal foundation having dislocations is used to obtain a crystal film of low dislocation density, a crystal substrate, and a semiconductor device. One side of a growth substrate ( 11 ) is provided with a crystal layer ( 13 ) with a buffer layer ( 12 ) in between. The crystal layer ( 13 ) has spaces ( 13   a ), ( 13   b ) in an end of each threading dislocation D 1  elongating from below. The threading dislocation D 1  is separated from the upper layer by the spaces ( 13   a ), ( 13   b ), so that each threading dislocation D 1  is blocked from propagating to the upper layer. When the displacement of the threading dislocation D 1  expressed by Burgers vector is preserved to develop another dislocation, the spaces ( 13   a ), ( 13   b ) vary the direction of its displacement. As a result, the upper layer above the spaces ( 13   a ), ( 13   b ) turns crystalline with a low dislocation density.

TECHNICAL FIELD

The present invention relates to a crystal film and a crystal substrate,and a semiconductor device using the same, and specifically to a crystalfilm made of nitride III-V compounds, a crystal substrate and asemiconductor device such as a laser diode.

RELATED ART

In recent years, a nitride III-V compound semiconductor made of Group 3Belements such as aluminum (Al), gallium (Ga), indium (In) or the likeand Group 5B elements including nitrogen (N) has drawn attention as amaterial capable of emitting light from a visible band ranging fromgreen to blue to a near ultraviolet band. As a result, a semiconductordevice such as a laser diode (LD) and a light emitting diode (LED) usingthe nitride III-V compound semiconductor is developed. Specifically,continuous oscillation is realized in the laser diode and an improvementin the crystalline of the nitride III-V compound semiconductor layer isdemanded to realize longer operating life.

However, a substrate suitable for crystal growth has not been achievedin the nitride III-V compound semiconductor. The nitride III-V compoundsemiconductor such as GaN has a smaller lattice constant than othersemiconductor crystals, so there is no common substrate having similarlattice constant and thermal expansion coefficient to the nitride III-Vcompound semiconductor. Only the GaN substrate with a lot of cracks anddislocations in the crystal is obtained, although this is best suitedfor the growth. Accordingly, various different substrates such assapphire (α-Al₂O₃) have been used instead. Dislocations due to thelattice mismatching are reduced by depositing a buffer layer of AlN orAl_(x)Ga_(1−x)N (0≦x≦1) at a low temperature of 900° C. or below on thesubstrate (Japanese Patent Laid-Open No. Sho 63-188938 and Publicationof Examined Application No. Hei 8-8217). However, obtaining a highquality crystal film has limitations and therefore, a technique forachieving a crystal film with lower threading dislocation density hasbeen demanded.

To achieve this, a technique for improving the crystalline has beenstudied and recently, a method of growing the crystal in the lateraldirection attracts attention. For example, Japanese Patent Laid-Open No.Hei 10-312971 discloses a method of laterally growing the upper layer ofthe crystal film on a two-dimensionally patterned mask with a stripeshape or the like, after growing the lower layer of the crystal film.With this method, dislocations from an opening of the mask to an upperlayer are crooked above the mask by the lateral growth and threadingdislocation density is reduced in, particularly, the upper part of themask in the upper layer. The publication also discloses that repeatingthe lateral growth several times to alternately displace the maskposition can further reduce the threading dislocation density.

In addition, a method in which a low dislocation density region isformed in a desired region by crooking dislocations taking advantage ofdifference in the growth rate according to the crystal growth face hasbeen proposed (refer to Japanese Patent Laid-Open No. Hei 11-130597, forexample).

Furthermore, as a technique using the lateral growth, the method ofgrowing the crystal film by using a seed crystal film formed on a growthsubstrate as a base has been proposed (MRS Internet J. Nitride Semicond.Res. 4S1, G3.38 (1999), MRS Internet J. Nitride Semicond. Res. 4S1, G4.9(1999) and Nakamura et al.; The 46th Spring Meeting 1999; The JapanSociety of Applied Physics and Related Societies, page 31-N-8, forexample). This method forms a region having a low threading dislocationdensity on the top surface because the crystal film grows in the lateraldirection from the side surface of the seed crystal film anddislocations in the crystal film are crooked.

A method of forming the region having little defects by re-growing thecrystal film after obtaining the recess structure by etching the seedcrystal film has been reported (Ishida et al.; The 46th Spring Meeting1999; The Japan Society of Applied Physics and Related Societies, page30-M17). The recess structure may further reduce the defects in thecrystal when depositing the silicon nitride (SiN_(x)) film on the sidesand the bottom surfaces (Ishibashi et al.; The 46th Spring Meeting 1999;The Japan Society of Applied Physics and Related Societies, page28-YQ-4). A method of forming an island shaped seed crystal byself-assembly with the treatment using silane (SiH₄) on the surface ofthe crystal film has been reported (H. Lahreche, P. Vennegues, B.Beaumont and P. Gibart; J. Crystal Growth 205, 245 (1999)). This methodfacilitates the formation of the seed crystal without an etching processor the like.

However, most of the above-described methods require a mask formationstep when forming the mask or seed crystal film and crystal growth morethan once. As a result, a lot of processes are required and this causesa problem with productivity.

The patterning of the mask or seed crystal film is performed regardlessof the dislocation distribution on the surface, so dislocations arepropagated from the region between the masks or the top surface of theseed crystal film. Moreover, dislocations themselves are crooked andremain in the crystal. Therefore, dislocations are not reduced unlessdislocations intersect with each other to combine the displacement.Dislocations may be shifted to the displacement of another direction, sodislocations do not always counteract even when dislocations intersectwith each other. This reveals that the conventional technique using thelateral growth has a limit of reduction in the dislocation density.

The crystal substrate fabricated with the above-described methods hasthreading dislocations extended from a mask gap or the crystal film andthe connecting portion on the top surface thereof. In general, thespaces of the mask and the crystal film are constant and threadingdislocations occur periodically corresponding to the spaces.Accordingly, in order to fabricate the semiconductor device with thecrystal having little dislocations, the semiconductor layer is formed bygrowing the major functions thereof (a light emitting region in a laser,for example) in a region having a low threading dislocation density inthe crystal substrate as described above to avoid the fatal dislocationsfor the device. To achieve this, each formation region of the substrateand the device needs to be aligned to a position with extremely goodprecision. This has resulted in alignment problems and limits the sizeof the device.

The present invention has been achieved in view of the above problems.It is an object of the invention to provide a crystal film and a crystalsubstrate capable of reducing the dislocation density effectively and asemiconductor device using the same.

SUMMARY OF THE INVENTION

A crystal film of an embodiment of the invention is grown on a baselayer having dislocations, wherein a space corresponding to an end of adislocation to be propagated from the base layer to an upper layer isformed.

Another crystal film of an embodiment of the invention comprises adislocation blocking portion for blocking the propagation of thedislocations corresponding to an end of a dislocation to be propagatedfrom the base layer to an upper layer.

A crystal substrate and a semiconductor device of and embodiment of theinvention comprise a crystal film formed with a space or a dislocationblocking portion for blocking the propagation of the dislocations in theposition corresponding to an end of a dislocation to be propagated froma base layer to an upper layer.

In a crystal film of an embodiment of the invention, spaces are providedon each end of dislocation, so the dislocation density in the portionformed above the spaces is reduced.

In another crystal film of an embodiment of the invention, a dislocationblocking portion is provided on each end of dislocation. As a result,the dislocation density in the portion formed above the spaces isreduced.

The crystal substrate and the semiconductor device of an embodiment ofthe invention comprise the crystal film of one of the embodiments of theinvention, so the dislocation density on the upper layers on thesubstrate is reduced.

Other and further objects, features and advantages of the invention willappear more fully from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B show the structure of the crystal substrate according toa first embodiment of the invention. FIG. 1A is a cross sectional viewand FIG. 1B is a view showing the occurrence of dislocations of thecrystal substrate shown in FIG. 1A.

FIG. 2 is a view for explaining a method of manufacturing the crystalsubstrate shown in FIGS. 1A and 1B.

FIG. 3 is a view for explaining another method of manufacturing thecrystal substrate shown in FIGS. 1A and 1B.

FIGS. 4A and 4B show the structure of the crystal substrate according toa second embodiment of the invention. FIG. 4A is a cross sectional viewand FIG. 4B is a view showing the occurrence of dislocations of thecrystal substrate shown in FIG. 4A.

FIGS. 5A and 5B are views for explaining a method of manufacturing thecrystal substrate shown in FIGS. 4A and 4B.

FIGS. 6A and 6B show the structure of the crystal substrate according toa third embodiment of the invention. FIG. 6A is a cross sectional viewand FIG. 6B is a view showing the occurrence of dislocations of thecrystal substrate shown in FIG. 6A.

FIG. 7 is a view for explaining a method of manufacturing the crystalsubstrate shown in FIGS. 6A and 6B.

FIGS. 8A and 8B show the structure of the crystal substrate according toa fourth embodiment of the invention. FIG. 8A is a cross sectional viewand FIG. 8B is a view showing the occurrence of dislocations of thecrystal substrate shown in FIG. 8A.

FIG. 9 is a sectional view of the structure of the crystal substrateaccording to a fifth embodiment of the invention.

FIG. 10 is a view showing the structure of the substrate according to asixth embodiment of the invention.

FIGS. 11A and 11B are views for explaining a method of manufacturing thecrystal substrate shown in FIG. 10.

FIGS. 12A to 12C are views for explaining the steps of the manufacturingprocess continued from FIG. 11B.

FIG. 13 is a sectional view showing the structure of the semiconductordevice utilizing the crystal substrate shown in FIGS. 8A and 8B.

FIG. 14 is a sectional view showing the structure of the semiconductordevice utilizing the crystal substrate according to the first embodimentof the invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described in more detailbelow referring to the accompanying drawings.

First Embodiment

FIG. 1A shows a sectional structure of a crystal substrate 10 accordingto a first embodiment of the invention. FIG. 1B is a view showingdislocations of the crystal substrate 10 shown in FIG. 1A. In thecrystal substrate 10, a crystal layer 13 is formed on a growth substrate11 with a buffer layer 12 in between.

The growth substrate 11 is made of a crystalline material such assapphire, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide(GaAs), silicon (Si), a composite oxide of magnesium and aluminum(MgAl₂O₄; spinel), or a composite oxide of lithium and gallium (LiGaO₂),and has a thickness of 400 μm, for example. The growth substrate 11 maybe made of III-V compounds including at least one element selected fromGroup 3B elements and at least arsenic (As) and phosphorus (P) selectedfrom Group 5B elements. The crystal substrate having dislocations arewidely applicable as the growth substrate 11.

The buffer layer 12 is a core layer for growing the crystal layer 13 andis formed of GaN having a thickness of 30 nm, for example. The bufferlayer 12 has threading dislocations D₁ propagate to the crystal layer13. Threading dislocations D₁ are caused by the lattice mismatching ordifference of the thermal expansion coefficient between the growthsubstrate 11 and the buffer layer 12 and its density is about 3×10⁸cm⁻², for example.

The crystal layer 13 is formed of a crystal of the wurtzite structure.An example of a crystal of the wurtzite structure is nitride III-Vcompounds including at least one element selected from Group 3B elementsand at least nitrogen (N) selected from Group 5B elements in the shortperiodic table. The crystal layer 13 corresponds to an example of the“crystal film” of the invention.

In the crystal layer 13, the threading dislocations D₁ penetrate fromthe buffer layer 12 formed thereunder, and a space 13 a is formed oneach end of the individual threading dislocations D₁. The spaces 13 amay be connected to each other dependent upon the density of threadingdislocations D₁, thereby forming a space 13 b. Dislocations penetrate tothe bottom of the spaces 13 a and 13 b and are prevented frompropagating to the upper layers on the spaces 13 a and 13 b.

The shape of the space 13 a is polyangular pyramid with the portionpenetrating to the threading dislocation D₁ as the apex or cone-shapedhollow with the portion penetrating to the threading dislocation D₁ asthe center. An example of the polyangular pyramid is an invertedsix-sided pyramid composed of six crystal faces (1101) (S faces). Thecombined spaces 13 a form a shape of the space 13 b. The cross sectionalsurface of the space 13 b is the shape in which the inverted triangleswith the portion penetrating to the threading dislocation D₁ as thecenter continues like the teeth of a saw or the shape in which the spaceof the cone-shaped hollow with the portion penetrating to the threadingdislocation D₁ as the center continues. Assuming the density ofthreading dislocations D₁ penetrating to the spaces 13 a and 13 b is b,the average distance between each threading dislocation D₁ becomesb^(−1/2), so when forming the space 13 b by combining the individualspaces 13 a corresponding to each threading dislocation D₁, each space13 a needs to be formed to have a diameter of b^(−1/2) or more, forinstance.

When growing the crystal in the lateral direction, vacancy may be formedin the connecting portion of the crystals grown in the lateraldirection. This vacancy is different from the spaces 13 a and 13 b. Thespaces 13 a and 13 b are the region where the crystal is discontinuousin three dimensions and the inside thereof may be a vacuum.Alternatively, a no-crystallized amorphous-material may be left at leastin part, or gas or liquid may be filled, or these states may besimultaneous.

In the crystal layer 13, when new dislocations occur from the spaces 13a and 13 b during the crystal growth, the new dislocations each havedisplacement equivalent to the sum of the displacement of the threadingdislocations D₁, that is, the sum of the Burgers vector. However, in thespace 13 b, when the total sum of the displacement of threadingdislocations D₁ is 0, no dislocations occur and the propagation ofdislocations to the upper layers can be suppressed. Further, when thesum of the displacement of threading dislocations D₁ is not 0, thedisplacement of threading dislocations D₁ is generally synthesized tocouple threading dislocations D₁. Therefore, the number of newdislocations occurring from the spaces 13 a and 13 b is smaller thanthat of threading dislocations D₁. The upper parts of the spaces 13 aand 13 b are grown in the lateral direction as described hereinafter, sothe direction of the displacement of threading dislocations D₁ ischanged in the crystal growth process and new dislocations D₂ can bepropagated in the lateral direction. This enables the suppression of thepropagation of dislocations above the spaces 13 a and 13 b. As a result,the dislocation density in the upper layers on the crystal layer 13 islower than that of the lower layers. When the diameter of the space 13 bcorresponding to each threading dislocation D₁ is set to 30 nm or more,more dislocations can be synthesized and more Burgers vectors canceleach other.

The crystal substrate 10 is fabricated as follows.

First, as shown in FIG. 2, the growth substrate 11 is prepared. Thebuffer layer 12 made of GaN is grown on a surface of the growthsubstrate 11 (when the growth substrate 11 is made of sapphire, it isgrown on the c face, for example) by, for example, MOCVD (MetalorganicChemical Vapor Deposition). At this time, the temperature (growthtemperature) of the growth substrate 11 is 520° C., for example. On thebuffer layer 12, a lower layer 13 c of the crystal layer 13 made of, forexample, nitride III-V compounds is grown at 1000° C. The threadingdislocations D₁ exist in the lower layer 13 c.

When performing MOCVD, trimethyl gallium ((CH₃)₃Ga) as a source gas ofgallium, trimethyl aluminum ((CH₃)₃Al) as a source gas of aluminum,trimethyl indium ((CH₃)₃In) as a source gas of indium, trimethyl boron((CH₃)₃B) as a source gas of boron are used as a source gas of Group 3Belements, for example. As a source gas of Group 5B elements, ammonia(NH₃) is used as a source gas of nitrogen, for instance. Examples of acarrier gas are hydrogen (H₂) and nitrogen (N₂). When growing thecrystal layer 13 (the lower layer 13 c and an upper layer describedlater), impurities such as silicon (Si) or magnesium (Mg) may be added,if necessary. In this case, monosilane (SiH₄) is used as a source gas ofsilicon and bis=cyclopentadienyl magnesium ((C₅H₅)₂Mg) is used as asource gas of magnesium, for example.

Next, the supply of the source gas of Group 3B elements is stopped andheat treatment is performed at 1000° C. or above (for example, 1020° C.)for determined time (for example, three minutes) in the atmospherecontaining hydrogen. At this time, etching by heat and hydrogen gasintensively proceeds around the threading dislocations D₁ due to theweak strength. Accordingly, etch pits 13 a ₁ and 13 b ₁ are formed onthe surface of the lower layer 13 c spontaneously corresponding to eachthreading dislocation D₁. The meaning of “spontaneously corresponding”here is that the etch pits 13 a ₁ and 13 b ₁ connect to the threadingdislocations D₁ without patterning by lithography or the like. It ispreferable that the etch pits 13 a ₁ and 13 b ₁ are formed by adjustingthe growth conditions to have the diameter corresponding to thedislocation density b of b^(−1/2) or more and become the etch pit 13 b ₁connecting to the plural threading dislocations D₁. The depth of theetch pits 13 a ₁ and 13 b ₁ are 30 nm or more and preferably 100 nm ormore. Etching may be performed on the interface with the growthsubstrate 11.

Then the supply of the source gas of Group 3B elements is restarted andthe upper layer of the crystal layer 13 is grown. The growth rate on thesurface of the lower layer 13 c is higher than the upper of the etchpits 13 a ₁ and 13 b ₁, and the lateral growth proceeds to cover theetch pits 13 a ₁ and 13 b ₁ to form the spaces 13 a and 13 b. Thereby,the spaces 13 a and 13 b are provided on an end of each threadingdislocation D₁ and the threading dislocations D₁ are blocked from theupper layer.

When the sum of the displacement of threading dislocations D₁ connect tothe space 13 b (etch pit 13 b ₁) is 0, no new dislocations occur. Evenwhen the sum of the displacement of threading dislocations D₁ is not 0,the displacement of threading dislocations D₁ is generally synthesizedto couple the threading dislocations D₁. Therefore, the number of newdislocations occurring from the space 13 b is smaller than that ofthreading dislocations D₁. Further, when the direction of thedisplacement of threading dislocations D₁ is changed due to the spaces13 a and 13 b (etch pits 13 a ₁ and 13 b ₁), new dislocations occurringfrom the spaces 13 a and 13 b (the dislocations D₂ shown in FIG. 1B, forexample) can be propagated in the lateral direction. This reduces thedislocation density in the region from the spaces 13 a and 13 b to thesurface of the crystal layer 13 (that is, the upper layer).

Growing the upper layer more than a certain time substantially smoothesthe growth surface. Thereby, the crystal layer 13 and the crystalsubstrate 10 shown in FIGS. 1A and 1B are obtained.

As described, in the embodiment, the spaces 13 a and 13 b are providedin the crystal layer 13 to correspond to each threading dislocation D₁.As a result, the spaces 13 a and 13 b prevent the propagation of thethreading dislocations D₁ to the upper layer and the dislocation densityin the upper layer can be reduced. This enables to easily obtain thecrystal layer 13 having uniformly reduced dislocation density in theupper layer. Specifically, in the space 13 b, each displacement ofthreading dislocations D₁ is synthesized with high ratio anddislocations can be reduced efficiently.

As described, there has been a problem that dislocations are propagatedfrom the mask or the seed crystal because conventionally the mask or theseed crystal is patterned regardless of the dislocation distribution.However, this problem is solved in the embodiment. When thesemiconductor device is manufactured by use of such a crystal substrate10, the alignment of the substrate is not required. From this viewpoint,it is found that in the crystal substrate of the invention, dislocationsare effectively reduced compared to the conventional crystal substrate.

The etch pits 13 a ₁ and 13 b ₁, and the spaces 13 a and 13 b arespontaneously formed, so the threading dislocation density in the upperlayer of the crystal layer 13 is reduced easily and efficiently.Furthermore, the etch pits 13 a ₁ and 13 b ₁ are formed in the MOCVDdevice. As a result, the crystal layer 13 is easily obtained with fewermanufacturing steps.

(Modification)

In the above first embodiment, the spaces 13 a and 13 b are formedutilizing the etch pits 13 a ₁ and 13 b ₁. However, as shown in FIG. 3,the growth pits 13 a ₂ and 13 b ₂ may be formed instead of the etch pits13 a ₁ and 13 b ₁.

The growth pits 13 a ₂ and 13 b ₂ are formed as follows, for example.After growing the lower layer 13 c with a growth temperature of 1000° C.or higher, the supply of the source gas of Group 3B elements is stoppedto reduce the growth temperature to 850° C. The supply of the source gasof Group 3B elements is again started to grow a middle layer 13 d of thecrystal layer 13 10 nm or more, preferably 30 nm or more, and morepreferably 50 nm or more, for example 100 nm. At that time, the growthpits 13 a ₂ and 13 b ₂ are spontaneously formed in the middle layer 13 dcorresponding to each threading dislocation D₁. The depth in thelaminate direction is 10 nm to 100 nm, for instance. The growth pits 13a ₂ and 13 b ₂ are spontaneously formed corresponding to the threadingdislocations D₁ because the crystal film grown with the growthtemperature of 1000° C. or lower by MOCVD tends to generate the growthpits in general. The shape of the growth pits 13 a ₂ and 13 b ₂ is thesame as that of the etch pits 13 a ₁ and 13 b ₁. The growth pits 13 a ₂and 13 b ₂ may be formed by growing the middle layer 13 d with rapidlyreduced growth rate. To change the growth rate, the supply of Group 3Belements source gas may be changed or the ratio of the supply of Group3B elements source gas and the supply of Group 5B elements source gasmay be changed. In addition, the growth pits 13 a ₂ and 13 b ₂ may beformed by changing the pressure (growth pressure) in the MOCVD deviceduring the growth. The above described growth conditions may besimultaneously changed.

Next, the crystal layer 13 is grown to cover the upper part of thegrowth pits 13 a ₂ and 13 b ₂ formed as described above to form thespace (refer to FIGS. 1A and 1B). As a method of forming the space, thegrowth rate is rapidly increased to stimulate the lateral growth,thereby the crystal is grown to cover the upper part of the growth pits13 a ₂ and 13 b ₂ and the space is formed inside the crystal layer 13.To change the growth rate, the supply of Group 3B elements source gasmay be changed or the ratio of the supply of Group 3B elements sourcegas and the supply of Group 5B elements source gas may be changed. Thegrowth pits 13 a ₂ and 13 b ₂ may be formed by changing the pressure(growth pressure) in the MOCVD device during the growth. The abovedescribed growth conditions may be simultaneously changed.

Other embodiments will be described in the following. The same numeralswill be given to the same component as the first embodiment and thedetailed explanation thereof will be omitted.

Second Embodiment

FIG. 4A shows a sectional structure of a crystal substrate 20 of asecond embodiment. FIG. 4B schematically shows dislocations of thecrystal substrate 20 shown in FIG. 4A. The crystal substrate 20 has thesame structure as the crystal substrate 10 of the first embodimentexcept that the crystal substrate 20 comprises a crystal layer 23instead of the crystal layer 13 of the first embodiment.

The crystal layer 23 of the embodiment has spaces 23 a and 23 b like thespaces 13 a and 13 b of the first embodiment. However, a coat film 21including, for example at least one of oxygen, nitrogen, fluorine orcarbon is provided on the inner surface of the spaces 23 a and 23 b. Thecoat film 21 is preferably amorphous to avoid the growth of the crystalthereon. As the material of the coat film 21, a metal material such asaluminum (Al), gallium (Ga), indium (In), magnesium (Mg), zirconium (Zr)or titanium (Ti), silicon (Si) oxide, nitride, fluoride, and carbide arecited. The above metal materials, simple substance of silicon, resist orother organic materials may be used to form the coat film 21.

To form the crystal substrate 20, first, as shown in FIG. 5A, etch pits23 a ₁ and 23 b ₁ are formed like the first embodiment, for instance,and after that, the supply of the source gases of Group 3B elements andGroup 5B elements is stopped and the gas containing silicon and oxygenis supplied to the etch pits 23 a ₁ and 23 b _(i). Thereby, the coatfilm 21 including silicon and oxygen is formed in the etch pits 23 a ₁and 23 b _(i). At this time, it is preferable that the thickness of thecoat film 21 becomes thicker closer to the depth direction of the etchpits 23 a ₁ and 23 b ₁.

The coat film 21 may be formed of the materials in addition to theabove-described materials. For example, the coat film 21 made of galliumoxide may be formed by supplying the gas containing gallium and oxygen,and the coat film 21 made of silicon nitride may be formed by supplyingthe gas containing silicon and nitrogen gas.

After forming the coat film 21, as shown in FIG. 5B, dry etching such asRIE is performed in the atmosphere containing hydrogen, for instance. Atthis time, since the surface of a lower layer 23 c is in contact withetching gas, etching is more proceeded here than the etch pits 23 a ₁and 23 b _(i). Accordingly, the parts formed on the lower layer 23 c inthe coat film 21 are selectively removed by etching. When the thicknessof the coat film 21 becomes thicker in the depth direction of the etchpits 23 a ₁ and 23 b ₁, the coat film 21 can be removed easily. Here,etching is not limited to dry etching and wet etching may be also used.

Like the first embodiment, for example, the upper layer of the crystallayer 23 is grown to form the spaces 23 a and 23 b on the etch pits 23 a₁ and 23 b ₁. Thereby, the crystal layer 23 and crystal substrate 20shown in FIGS. 4A and 4B are achieved. Here, the coat film 21 isprovided on the inner surface of the etch pits 23 a ₁ and 23 b ₁, so thecontrol of the growth conditions for forming the spaces 23 a and 23 bcan be facilitated.

As described, in the embodiment, the coat film 21 is provided on thesurface of the etch pits 23 a ₁ and 23 b ₁. As a result, the growthconditions at the time of forming the spaces 23 a and 23 b by growingthe upper layer of the crystal layer 23 can be eased and the formationthereof can be facilitated.

Third Embodiment

FIG. 6A shows a sectional structure of a crystal substrate 30 of a thirdembodiment. FIG. 6B schematically shows the crystal substrate 30 shownin FIG. 6A. The crystal substrate 30 has the same structure as thecrystal substrate 10 of the first embodiment except that a crystal layer33 is provided instead of the crystal layer 13 of the first embodiment.The crystal substrate 30 is fabricated as described hereinbelow.

First, as shown in FIG. 7, like the first embodiment, etch pits 33 a ₁and 33 b ₁ are formed on a surface of a lower layer 33 c. Subsequently,at least one of oxidation, nitridation, fuluoridation and carbonizationis performed on the surface of the lower layer 33 c including the etchpits 33 a ₁ and 33 b ₁ to form a surface treatment region 33 c ₁. Thesurface treatment region 33 c ₁ has a thickness of, for example 1 nm inthe thickness direction. Specifically, the surface treatment region 33 c₁ made of oxide of Group 3B elements is formed by stopping the supply ofthe source gases of Group 3B elements and nitrogen and supplying gascontaining oxygen to react oxygen with Group 3B elements in the lowerlayer 33 c. The surface treatment region 33 c ₁ made of silicon nitridemay be formed by supplying gas containing silicon to react silicon withnitrogen in the lower layer 33 c. Further, the surface treatment region33 c ₁ made of gallium fluoride or gallium carbide may be formed bysupplying gas containing fluorine or carbon to react fluorine or carbonwith gallium in the lower layer 33 c.

Next, for example, like the second embodiment, dry etching or wetetching is performed to selectively remove part of the surface treatmentregion 33 c ₁. The following steps are the same as the secondembodiment. Thereby, the crystal layer 33 and the crystal substrate 30shown in FIGS. 6A and 6B are achieved.

As described, in the embodiment, the surface treatment region 33 c ₁ isprovided by performing the surface treatment on the surface of the etchpits 33 a ₁ and 33 b ₁. As a result, the growth conditions at the timeof forming the spaces 33 a and 33 b by growing the upper layer of thecrystal layer 33 can be eased and the formation thereof can befacilitated.

Fourth Embodiment

FIG. 8A shows a sectional structure of a crystal substrate 40 of afourth embodiment. FIG. 8B schematically shows the crystal substrate 40shown in FIG. 8A. The crystal substrate 40 comprises a mask 41 on asurface on which the spaces 13 a and 13 b are formed in the crystallayer 13 of the first embodiment. The crystal substrate 40 is fabricatedas follows.

As shown in FIGS. 8A and 8B, first, the lower layer 13 c is formed and asilicon oxide (SiO_(x)) film, a silicon nitride (SiN_(y)) film orlaminated film thereof are formed thereon. After that, dry etching suchas RIE (Reactive Ion Etching) is performed and the mask 41 which ispatterned in stripe shape is formed. At that time, the width of the mask41 is, for example, 5 μm and the space therebetween is 50 nm to 10 mm,for instance. The space may be equal or unequal. The pattern of the mask41 may be other than stripe shape, for example, rectangular shape,lattice shape, hexagonal shape, triangular shape or circular shape.

Next, the etch pits 13 a _(i) and 13 b ₁ are formed like the firstembodiment. Here, the etch pits 13 a ₁ and 13 b ₁ are formed by etchingthe surface in the opening region except mainly the mask 41. After that,the upper layer of the crystal layer 13 is grown to form the space 13 b.Here, the upper layer starts to grow in the opening region between themasks 41, and to laterally grow on the mask 41. At that time, thethreading dislocations D₁ are blocked by the space 13 b in the openingregion, so the propagation of the threading dislocations D₁ on the mask41 is also reduced. Therefore, the whole upper layer has a lowdislocation density. Thereby, the crystal layer 13 and the crystalsubstrate 40 are achieved.

As described, in the embodiment, the space 13 b is provided. As aresult, the crystal substrate 40 having uniformly low threadingdislocation density can be obtained regardless of the position of themask 41. Here, the upper layer is laterally grown with the mask 41 inbetween on the lower layer 13 c, so even the threading dislocations D₁not blocked by the space 13 b exist, the threading dislocations D₁ arecrooked in the lateral direction. Therefore, the dislocation density ofthe upper layer is further reduced.

The mask 41 reduces the formation region of the etch pits 13 a ₁ and 13b ₁, so the growth conditions of the upper layer such as an increase inthe growth rate can be tighten. The order of formation of the etch pits13 a ₁ and 13 b ₁ and the mask 41 can be reversed and the formationposition thereof can be open.

Fifth Embodiment

FIG. 9 shows a sectional structure of a crystal substrate 50 of a fifthembodiment. The lower layer of the crystal substrate 50 is formed bylateral growth on a basis of a seed crystal 51 in the crystal layer 13of the first embodiment. The crystal substrate 50 is fabricated asfollows.

First, the buffer layer 12 is grown on the growth substrate 11 and then2 μm-thick seed crystal film made of GaN is grown by MOCVD on the bufferlayer 12, for instance. Subsequently, on the seed crystal film, asilicon nitride film or a silicon dioxide film (not shown) which ispatterned in stripe shape is formed. Then, RIE is performed using thepattern as a mask and an unnecessary part in the seed crystal film isremoved. RIE is again performed by using the same mask and a groove 11 ais formed in the growth substrate 11 so that the crystal at the time ofthe lateral growth is not in contact with the growth substrate 11. Afterthat, wet etching is performed, for example and the mask (not shown) isremoved. Thereby, the seed crystal 51 is formed.

Using the seed crystal 51 as a base, the lower layer of the crystallayer 13 is grown by MOCVD, for example. The growth of the lower layeradvances from the top surface of the seed crystal 51 to the upwarddirection and from the sidewalls to the lateral direction. At that time,the threading dislocations D₁ are propagated to the top of the seedcrystal 51. In other parts, dislocations occur in the connecting portionwith the lateral growth. However, almost no threading dislocations D₁exist. The lateral growth rate is larger than growth rate in the topsurface, so the growth surface becomes substantially flat as certaintime advances.

Similar to the first embodiment, the etch pits 13 a ₁ and 13 b ₁ areformed on a surface of the lower layer. As described above, thethreading dislocation density is high in the upper part of the seedcrystal 51, so a lot of etch pits 13 a ₁ and 13 b ₁ are formed. Inaddition, the etch pits 13 a ₁ and 13 b ₁ are formed corresponding tothe threading dislocations D₁ generated in the connecting portion. Theupper layer of the crystal layer 13 is grown to form the spaces 13 a and13 b in the position of the etch pits 13 a ₁ and 13 b ₁. Further growthof the upper layer substantially smoothes the growth surface. Thereby,the crystal layer 13 and the crystal substrate 50 are achieved.

As described, the crystal layer 13 is the lateral growth regionutilizing the seed crystal 51. Further, the threading dislocationdensity is low in the lower layer. This enables to reduce the threadingdislocation density in the upper layer.

Sixth Embodiment

FIG. 10 schematically shows a crystal substrate 60 of a sixthembodiment. The crystal substrate 60 has the same structure as thecrystal substrate 10 of the first embodiment except that a crystal layer63 is provided instead of the crystal layer 13 of the first embodiment.The crystal substrate 60 is fabricated as follows.

First, as shown in FIG. 11A, like the first embodiment, a lower layer 63a is grown and then the supply of the source gas of Group 3B elements isstopped to lower the growth temperature to 750° C. After that, thesource gases of gallium and indium are supplied at appropriate ratio togrow a middle layer 63 b made of In_(p)Ga_(1−p)N mix crystal (p≧0.05) 5nm on the lower layer 63 a. When InGaN mix crystal having the indiumcomposition ratio of 5% or more is grown, as shown in FIG. 11B, metalindium is deposited corresponding to the threading dislocations D₁spontaneously and a dislocation blocking portion 63 c made of metalindium is formed.

As shown in FIGS. 12A to 12C, for example, the supply of the source gasof indium is stopped and the growth temperature is raised to 1020° C.,and an upper layer 63 d made of nitride III-V compounds is grown on themiddle layer 63 b. The crystal growth of GaN does not easily occur fromthe dislocation blocking portion 63 c compared to the middle layer 63 band the grown upper layer 63 d, so the lateral growth from the upperlayer 63 d formed on the dislocation blocking portion 63 c is advanced(FIG. 12B) and the propagation of threading dislocations D₁ is blocked.Further growth of the upper layer 63 d substantially smoothes the growthsurface (FIG. 12C), thereby the crystal layer 63 and the crystalsubstrate 60 are achieved.

As described, in the embodiment, the dislocation blocking portion 63 ccorresponding to each threading dislocation D₁ is provided in the middlelayer 63 b. As a result, the dislocation blocking portion 63 c blockseach threading dislocation D₁ and enables to form the upper layer withthe crystal having a low dislocation density. Therefore, the crystallayer 63 with simple structure and uniformly reduced threadingdislocation density in the upper layer can be obtained.

Here, the dislocation blocking portion 63 c is spontaneously formed. Asa result, the threading dislocation density in the upper layer of thecrystal layer 63 can be efficiently and easily reduced.

All crystal films and crystal substrates of the invention describedabove can be applicable to the semiconductor device. The crystal layers13 to 63 which are obtained by removing the growth substrate 11 from thecrystal substrates 10 to 60 of the embodiments or a thin film formed ofpart of the crystal layers 13 to 63 can be used for the semiconductordevice as the nitride III-V compound substrate. In this case, the growthsubstrate 11 and the buffer layer 12 are removed by grinding, dryetching, wet etching or the like. The spaces 13 a and 13 b aredistributed in planar shape in the crystal layer 13 of the firstembodiment, so the mechanical strength in this part is weak. Therefore,the crystal layer 13 may be divided in this face and the lower layer andtherebelow may be removed. Laser irradiation, lamp irradiation,ultrasonic wave application, quenching or rapid heating is performed todivide the crystal layer 13. In addition, the crystal layer 13 may bemechanically deformed and the upper layer separated by use of the spaces13 a and 13 b. Further, after the separation of the upper layer, theseparation surface of the upper layer can be polished to form thecrystal layer (crystal film) including no spaces 13 a and 13 b. Thepolishing process of the separation surface may be carried out in thecrystal layer (crystal film) level or after forming the device such as alaser diode on the crystal film as described later. This is applied whenthe crystal substrate 20 of the second embodiment to the crystalsubstrate 50 of the fifth embodiment is used.

Seventh Embodiment

In a seventh embodiment, a semiconductor device using the crystalsubstrate fabricated in the above embodiments will be described. Anycrystal substrate of the above embodiments is similarly used because itis unnecessary to consider the difference of the internal structure ofthe crystal substrate. Therefore, as an example, a laser diode using thecrystal substrate 40 will be described here.

FIG. 13 shows a sectional structure of a laser diode 1 using the crystalsubstrate 40. The laser diode 1 is a SCH (Separate ConfinementHeterostructure) structure of ridge waveguide. A semiconductor layer 100comprising an n-side contact layer 101, an n-type cladding layer 102, ann-type guide layer 103, an active layer 104, a crystal antidegradationlayer 105, a p-type guide layer 106, a p-type cladding layer 107 and ap-side contact layer 108 are formed on the crystal substrate 40 on theside where the crystal layer 13 is formed. The crystal substrate 40comprises the growth substrate 11 made of sapphire with a thickness of400 μm, the buffer layer 12 made of GaN with a thickness of 30 nm andthe crystal layer 13 made of GaN with a thickness of 2 μm. The crystalsubstrate 40 is provided with the space 13 b between the masks 41, sothe threading dislocation density in the upper layer is uniformly low.

The semiconductor layer 100 has the structure as follows, for instance.The n-side contact layer 101 has a thickness of 2 μm and formed of ann-type GaN doped with silicon as an n-type impurity. The n-type claddinglayer 102 has a thickness of 1 μm and formed of an n-type AlGaN mixcrystal doped with silicon as an n-type impurity. The n-type guide layer103 has a thickness of 0.1 μm and formed of an n-type GaN doped withsilicon as an n-type impurity. The active layer 104 has a thickness of30 nm and a multiple quantum well structure laminating Ga_(x)In_(1−x)Nmix crystal layer and Ga_(y)In_(1−y)N (x≠y) mix crystal layer.

The crystal antidegradation layer 105 has a thickness of 20 nm andformed of a p-type AlGaN mix crystal doped with magnesium as a p-typeimpurity. The p-type guide layer 106 has a thickness of 0.1 μm andformed of a p-type GaN doped with magnesium as a p-type impurity. Thep-type cladding layer 107 has a thickness of 0.8 μm and formed of ap-type AlGaN mix crystal doped with magnesium as a p-type impurity. Thep-side contact layer 108 has a thickness of 0.5 μm and formed of ap-type GaN doped with magnesium as a p-type impurity. Part of the p-sidecontact layer 108 and the p-type cladding layer 107 is the ridgestructure and constitute the current confinement part. Therefore, thepart corresponding to the current confinement part in the active layer104 is a light-emitting portion.

Here, each layer from the n-type cladding layer 102 to the p-sidecontact layer 108 is stacked on part of the n-side contact layer 101.The laminated part has a stripe shape.

The surfaces of the n-side contact layer 101 through the p-side contactlayer 108 are covered with an insulating film 111 made of, for example,silicon dioxide. The openings are formed in the insulating film 111above the n-side contact layer 101 and the p-side contact layer 108. Ann-side electrode 112 and a p-side electrode 113 are respectively formedin the openings. The n-side electrode 112 has a structure where titanium(Ti) and aluminum (Al) are laminated in this order, for example and isin electrical contact with the n-side contact layer 101. The p-sideelectrode 113 has a structure that palladium (Pd), platinum (Pt) andgold (Au) are laminated in this order, for example and is in electricalcontact with the p-side contact layer 108.

In the laser diode 1, a pair of side surfaces perpendicular to theelongated direction of the semiconductor layer 100 and facing each otherare resonator end face, and a pair of reflector films are respectivelyformed thereon. A pair of reflector films are adjusted so that one ofthe reflector film has a low reflectance and the other reflector filmhas a high reflectance. Thereby, the light generated in the active layer104 is amplified by traveling between a pair of reflector films andemitted from one of the reflector film as a laser beam. The laser diode1 is housed in the package (not shown) when using.

The laser diode 1 is fabricated as follows, for example.

First, the crystal substrate 40 having a plurality of laser diodeformation regions is prepared and the n-side contact layer 101, then-type cladding layer 102, the n-type guide layer 103, the active layer104, the crystal antidegradation layer 105, the p-type guide layer 106,the p-type cladding layer 107 and the p-side contact layer 108 aresequentially grown thereon by, for example, MOCVD to form thesemiconductor layer 100. Generally, in order to prevent the degradationof light emitting property or improve the light emitting property, it ispreferable that dislocations are not propagated at least to the lightemitting portion and the light-emitting portion is a low dislocationdensity region. Here, the crystal substrate 40 whose surface has auniformly low dislocation density is used, so the number of dislocationspropagate to the semiconductor layer 100 is evenly reduced. Thereby, thelight-emitting portion becomes the low dislocation density region.

Subsequently, the p-side contact layer 108, the p-type cladding layer107, the p-type guide layer 106, the crystal antidegradation layer 105,the active layer 104, the n-type guide layer 103, the n-type claddinglayer 102 and the n-side contact layer 101 are partially andsequentially etched to expose the n-side contact layer 101 on thesurface. Next, a mask (not shown) is formed on the p-side contact layer108 and the p-side contact layer 108 and the p-type cladding layer 107are partially and selectively etched by use of the mask. Due to this,the top of the p-type cladding layer 107 and the p-side contact layer108 become ridge shaped to form the current confinement part.

The insulating film 111 made of silicon dioxide is formed on the wholeexposed surface by, for example, deposition. The opening is formed inthe insulating film 111 corresponding to the p-side contact layer 108 toexpose it on the surface. The opening is also formed in the insulatingfilm 111 on the region of the n-side contact layer 101 and titanium,aluminum, platinum and gold are sequentially deposited on the openingand are alloyed to form the n-side electrode 112, for instance.Palladium, platinum and gold are sequentially deposited to correspond tothe exposed p-side contact layer 108 to form the p-side electrode 113.

The growth substrate 11 is grinded to be a thickness of, for example, 80μm. After that, the crystal substrate 40 is divided in the directionorthogonal to the elongated direction of the current confinement part.Thereby, a pair of resonator end surfaces of each laser diode 1 areformed and the reflector films (not shown) are respectively formed onthe resonator end surfaces. Next, dependent upon each laser diode 1formation region, the crystal substrate 40 is divided in the elongateddirection of the current confinement part. Thereby, a plurality of laserdiode 1 shown in FIG. 13 is achieved. The formed laser diode 1 ismounted in the package (not shown), for instance.

In the laser diode 1, when a predetermined voltage is applied betweenthe n-side electrode 112 and the p-side electrode 113, current isapplied to the active layer 104 and light emission occurs due toelectron-hole recombination. Here, the semiconductor layer 100 is formedon the crystal layer 13 having a low dislocation density on the surfacethereof, so the dislocation density from the n-side contact layer 101 tothe p-side contact layer 108 is also low. Therefore, the laser diode 1is superior in the light emitting property and has a longer life.

In the embodiment, the semiconductor layer 100 is provided on thecrystal substrate 40 of the fourth embodiment. As a result, thesemiconductor layer 100 has a significantly low dislocation density andexcellent crystalline. Therefore, the laser diode 1 can prevent thedegradation of the light emitting property, extend the life and improvereliability.

The substrate with the low dislocation density can be obtained with easymanufacturing method by using the crystal substrate 40 of the fourthembodiment. Furthermore, the productivity of the laser diode 1 isimproved and the cost is reduced. The crystal substrate 40 has uniformlylow dislocations on the surface thereof, so the semiconductor layer 100can be formed on any regions on the surface of the crystal substrate 40.This eliminates the need to align the substrate. For comparison, in thecrystal substrate using the general lateral growth, a lot of threadingdislocations extended between the masks exist. So, the semiconductorlayer is processed after align the position to have the light emittingportion on the top of the mask while avoiding threading dislocations.

Eighth Embodiment

In an eighth embodiment, a semiconductor device utilizing the crystalfilm fabricated in each embodiments described above will be explained.The crystal film can be fabricated with any methods. Here, as anexample, a laser diode 2 in which the upper layer of the crystal layer13 obtained by dividing the crystal substrate 10 is used as a nitrideIII-V compound substrate 81 will be described. The laser diode 2 has thesame structure as the laser diode 1 except that current blocking layers120 are provided on the both sides of the current confinement part andexcept the structure of the p-side electrode 113 and the n-sideelectrode 112.

FIG. 14 shows a sectional structure of the laser diode 2 of the eighthembodiment. The laser diode 2 has a structure that from the n-sidecontact layer 101 to the p-side contact layer 108 are sequentiallylaminated on a surface of the nitride III-V compound substrate 81(abbreviated to substrate hereinbelow). The current blocking layers 120are provided on the both sides of the current confinement part and thep-side electrode 113 is formed on the whole surface of the p-sidecontact layer 108 and the current blocking layer 120. Further, then-side electrode 112 is formed on the backside of the substrate 81.

The substrate 81 is the substrate in which the growth substrate 11, thebuffer layer 12, the lower layer of the crystal layer 13 are removedfrom the crystal substrate 10 (FIG. 1). The surface distributing thespaces 13 a and 13 b has weak strength, so laser irradiation, lampirradiation, ultrasonic wave application, quenching or rapid heating isperformed thereon to divide the crystal layer 13 from this face and toremove the lower layer of the crystal layer 13 and therebelow, forexample. Besides, the upper layer of the crystal layer 13 may be dividedfrom the surface distributing the spaces 13 a and 13 b by mechanicallydeforming. The lower layer of the crystal layer 13 and therebelow can beremoved by performing grinding, dry etching or wet etching (chemicaletching) on the growth substrate 11.

The current blocking layer 120 keeps the insulation with thesurroundings and is formed of the n-type AlGaN mix crystal doped with ann-type impurity such as silicon. Therefore, in the laser diode 2, thepart corresponding to the current confinement part in the active layer104 is the light-emitting portion. The current blocking layer 120 isformed by re-growing on the p-type cladding layer 107 after making thetop of the p-type cladding layer 107 and the p-side contact layer 108ridge shape.

The laser diode 2 has the same structure as the general AlGaAs orAlGaInP laser diode provided with the electrode on the backside of thesubstrate and can be manufactured as the same process thereof. Forexample, after growing each layer of the semiconductor layer 100, thetop of the p-type cladding layer 107 and the p-side contact layer 108are processed to be ridge shaped, and a resist film is formed thereon.Then, the insulating film is formed on the whole surface of thesemiconductor layer 100 and is removed with the resist film thereon toform the current blocking layer 120 (lift-off). Further, the p-sideelectrode 113 is formed on the whole top surface of the current blockinglayer 120 and the n-side electrode 112 is formed on the backside of thesubstrate 81. The laser diode 2 fabricated as described above canutilize the same package as the general AlGaAs or AlGaInP laser diode.

Here, the semiconductor layer 100 is provided on the substrate 81 havinglow dislocation density. As a result, the dislocation density from then-side contact layer 101 to the p-side contact layer 108 is also low.Therefore, the laser diode 2 has a excellent light emitting property andlonger life.

As described, in the embodiment, the semiconductor layer 100 is providedon the substrate 81. As a result, the semiconductor layer 100 has anextremely low dislocation density and excellent crystalline. Therefore,the laser diode 2 can prevent the degradation of the light emittingproperty, realize longer life and improve reliability.

In addition, the conductive substrate 81 is used and the n-sideelectrode 112 is provided on the backside thereof. As a result, comparedto the laser diode 1, the structure is simplified and the massproductivity is excellent. Further, in the laser diode 2, the thicknessof the substrate 81 can be reduced. This can achieve simple laserstructure and reduction in size.

As described above, although the present invention is describedreferring to the embodiments, the present invention is not limited tothe embodiments, and can be variously modified. For example, in thesecond through fifth embodiments, the etch pits 13 a ₁ to 33 a ₁ and 13b ₁ to 33 b ₁ are formed and the spaces are formed by using these etchpits. However, growth pits 13 a ₂ and 13 b ₂ are formed instead of theetch pits 13 a ₁ to 33 a ₁ and 13 b ₁ to 33 b ₁ and the spaces 13 a and13 b may be formed by using growth pits. In the fourth and fifthembodiments, the spaces 13 a and 13 b are provided like the firstembodiment. However, the coat film 21 or the surface treatment region 33c may be provided like the second and the third embodiments. Theinvention can combine any kinds within the above-described embodiments.

In the embodiments, one space layer distributed on the surface isprovided. However, a plurality of space layers may be provided byperforming the etch pits (or growth pits) formation step and the crystalgrowth step twice or more respectively. Thereby, the dislocation densityin the upper layer of the crystal film can be further reducedefficiently.

In the embodiments, the crystal layers 13, 53, 63 and 73 made of nitrideIII-V compounds are described as an example. However, the crystal filmmay be formed of other III-V compounds such as GaAs or InP. Theinvention is similarly applicable to the crystal film, the crystalsubstrate other than the III-V compounds and the semiconductor deviceusing thereof.

In the seventh and the eighth embodiments, the laser diodes 1 and 2 aredescribed as the semiconductor device. However, the invention isapplicable to the other semiconductor device such as a light-emittingdiode or a field-effect transistor.

As described, according to the crystal film of the invention, the spacesare formed in each end of dislocation. As a result, the number ofdislocations propagated to the upper layer is reduced and thedislocation density in the upper layer is uniformly and effectivelyreduced. Specifically, according to the crystal film of the invention,the crystal film is divided in the surface distributing the spaces andis constituted of at least part of the upper layer. As a result, thecrystal thin film having homogenized and excellent crystalline can beobtained.

Further, according to the crystal film of one aspect of the invention,the dislocation blocking region for blocking the propagation ofdislocations is formed in each end of dislocation. As a result, eachdislocation is blocked and the dislocation density in the upper layer iseffectively and uniformly reduced.

Furthermore, the crystal substrate of the invention comprises thecrystal film of the invention. Therefore, the dislocation density on theupper surface can be effectively and uniformly reduced.

In addition, the semiconductor device of the invention comprises thecrystal film of the invention. Therefore, the performance and theproductivity can be improved.

Obviously many modifications and variations of the present invention arepossible in the light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims, the inventionmay be practiced otherwise than as specifically described.

1. A crystal film comprising: a crystal layer having a first layer andan upper layer, said first layer being between a base layer and saidupper layer, wherein a threading dislocation within said base layerpropagates into said first layer, wherein a pit extends into said firstlayer, said threading dislocation terminating at said pit, and whereinsaid upper layer covers said pit, the covered pit being a space betweensaid first layer and said upper layer.
 2. A crystal film according toclaim 1, wherein said first layer is a lower layer, said lower layer andsaid upper layer being of a same material.
 3. A crystal film accordingto claim 1, wherein said first layer includes a lower layer and a middlelayer, said lower layer being between said base layer and said middlelayer, and said middle layer being between said lower layer and saidupper layer.
 4. A crystal film according to claim 3, wherein saidthreading dislocation propagates into said lower layer, and said pitextends into said middle layer.
 5. A crystal film according to claim 3,wherein said lower layer, said middle layer, and said upper layer are ofa same material.
 6. A crystal film according to claim 1, wherein a coatfilm is on an inner surface of said space.
 7. A crystal film accordingto claim 6, wherein said coat film is an amorphous material.
 8. Acrystal film according to claim 6, wherein said coat film includes atleast one of oxygen, nitrogen, fluorine and carbon.
 9. A crystal filmaccording to claim 1, wherein a surface treatment region is on an innersurface of said space.
 10. A crystal film according to claim 9, whereinsaid surface treatment region includes at least one of oxygen, nitrogen,fluorine and carbon.
 11. A crystal film according to claim 1, wherein adislocation blocking portion is on an inner surface of said space.
 12. Acrystal film according to claim 11, wherein said dislocation blockingportion includes indium.
 13. A crystal film according to claim 1,wherein said base layer is between a growth substrate and the crystalfilm.
 14. A crystal film according to claim 1, wherein said threadingdislocation extends to an apex of said pit.